SEU-Tolerant SRAM Design Based on Current Monitoring
نویسندگان
چکیده
In this paper, we present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using Built-In Current Sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking i s performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error Correction.
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